Verilog operators and expressions

Introduction¶

Verilog supports a rich set of operators and expressions to model arithmetic, logical, and bitwise operations. Understanding these is crucial for writing efficient and synthesizable RTL code.

Types of Operators¶

Verilog operators can be grouped into the following categories:

1. Arithmetic Operators
2. Relational Operators
3. Logical Operators
4. Bitwise Operators
5. Reduction Operators
6. Shift Operators
7. Concatenation and Replication Operators
8. Conditional (Ternary) Operator

Arithmetic Operators¶

Used for addition, subtraction, multiplication, division, and modulus.

Example:

reg [7:0] a = 8'd10, b = 8'd3;
reg [7:0] sum, diff, prod, quot, rem;

always @(*) begin
  sum  = a + b;  // 13
  diff = a - b;  // 7
  prod = a * b;  // 30
  quot = a / b;  // 3
  rem  = a % b;  // 1
end

Relational Operators¶

Used to compare values, returning 1 (true) or 0 (false).

Example:

reg flag;
always @(*) begin
  flag = (a >= b); // 1 if a >= b, else 0
end

Logical Operators¶

Used for Boolean logic; operate on 1-bit true/false values.

Example:

reg a, b, result;
always @(*) begin
  result = a && b; // 1 if both a and b are 1
end

Bitwise Operators¶

Operate on each bit individually; used extensively in RTL.

Example:

reg [3:0] a = 4'b1010, b = 4'b1100, y;
always @(*) begin
  y = a & b;   // 1000
  y = a | b;   // 1110
  y = a ^ b;   // 0110
  y = ~a;      // 0101
end

Reduction Operators¶

Reduce multiple bits into a single-bit result.

Example:

reg [3:0] a = 4'b1101;
reg result;
always @(*) begin
  result = &a; // 1 if all bits are 1, else 0
end

Shift Operators¶

Used to shift bits left or right.

Concatenation & Replication¶

Concatenation¶

Combine multiple signals:

reg [3:0] a, b;
reg [7:0] y;
always @(*) begin
  y = {a, b}; // a occupies [7:4], b occupies [3:0]
end

Replication¶

Repeat a value multiple times:

reg [1:0] a = 2'b10;
reg [5:0] y;
always @(*) begin
  y = {3{a}}; // repeats a three times: 101010
end

Conditional (Ternary) Operator¶

The conditional (ternary) operator in Verilog is a compact and efficient way to implement decision-making logic within expressions. It has the general form:

<condition> ? <expression_if_true> : <expression_if_false>;

Single Condition Example¶

assign y = sel ? a : b;

Multi-condition example¶

assign out = (mode == 2'b00) ? in0 :
              (mode == 2'b01) ? in1 :
              (mode == 2'b10) ? in2 : in3;

Operator Precedence¶

Precedence affects how expressions are evaluated. Commonly:

1. ()
2. Unary: ! ~ & | ^
3. Multiplicative: * / %
4. Additive: + -
5. Shift: << >> <<< >>>
6. Relational: < <= > >=
7. Equality: == != === !==
8. Bitwise AND: &
9. Bitwise XOR/XNOR: ^ ^~ ~^
10. Bitwise OR: |
11. Logical AND: &&
12. Logical OR: ||
13. Conditional: ?:
14. Assignment: = <= += -= *= /= %= ...

Use parentheses "( )" to avoid ambiguity.

Summary¶